Search - quartus modelsim vhdl

[Other resource] Des2Sim

Description: 本文介绍了一个使用 VHDL 描述计数器的设计、综合、仿真的全过程，作为我这一段时间自学 FPGA/CPLD 的总结，如果有什么不正确的地方，敬请各位不幸看到这篇文章的大侠们指正，在此表示感谢。当然，这是一个非常简单的时序逻辑电路实例，主要是详细描述了一些软件的使用方法。文章中涉及的软件有Synplicity 公司出品的Synplify Pro 7.7.1； Altera 公司出品的 Quartus II 4.2；Mentor Graphics 公司出品的 ModelSim SE 6.0。
Platform: | Size: 1945930 | Author: 黄鹏曾 | Hits:

[Other] Quartus+II+++ModelSim+SE+++后仿真+++库文件.rar

Description: Mentor公司的ModelSim是业界最优秀的HDL语言仿真软件，它能提供友好的仿真环境，是业界唯一的单内核支持VHDL和Verilog混合仿真的仿真器。它采用直接优化的编译技术、Tcl/Tk技术、和单一内核仿真技术，编译仿真速度快，编译的代码与平台无关，便于保护IP核，个性化的图形界面和用户接口，为用户加快调错提供强有力的手段，是FPGA/ASIC设计的首选仿真软件。
Platform: | Size: 1009119 | Author: t613@163.com | Hits:

[VHDL-FPGA-Verilog] Modelsim

Description: 不错的Quartus II 与modelsim结合仿真简介笔记，较为适合初学者，希望对大家有帮助！
Platform: | Size: 1357824 | Author: 刘英 | Hits:

[VHDL-FPGA-Verilog] Des2Sim

Description: 本文介绍了一个使用 VHDL 描述计数器的设计、综合、仿真的全过程，作为我这一段时间自学 FPGA/CPLD 的总结，如果有什么不正确的地方，敬请各位不幸看到这篇文章的大侠们指正，在此表示感谢。当然，这是一个非常简单的时序逻辑电路实例，主要是详细描述了一些软件的使用方法。文章中涉及的软件有Synplicity 公司出品的Synplify Pro 7.7.1； Altera 公司出品的 Quartus II 4.2；Mentor Graphics 公司出品的 ModelSim SE 6.0。 -This article describes a VHDL description of the use of counter design, synthesis, simulation of the entire process, this time as my self-FPGA/CPLD summary, if what has not the right place, please see this article that, unfortunately, the heroes They correct me, wish to express my gratitude. Of course, this is a very simple example of sequential logic circuit is mainly a detailed description of a number of software usage. Article involved in the software company has produced Synplicity
Platform: | Size: 1945600 | Author: 黄鹏曾 | Hits:

[VHDL-FPGA-Verilog] QuartusIIandModelSim

Description: 本文主要描述了如何在QUARTUS II 中输入程序文件，生成网表及标准延时文件，然后通过 MODELSIM进行功能仿真与后仿真的过程，主要为图解，含全部代码及仿真波形。 -This article describes how to enter at QUARTUS II program file, generate netlists and standard delay file, and then through the ModelSim for functional simulation and post-simulation process, mainly for the diagrams, containing all the code and the simulation waveform.
Platform: | Size: 277504 | Author: 朱雯 | Hits:

[VHDL-FPGA-Verilog] Quartus_fft_ip_core

Description: Quartus中fft ip core的使用(modelsim 仿真FFT ip core 结合QUARTUS II 联合调试)-Fft ip core in Quartus use (modelsim simulation FFT ip core integration QUARTUS II Joint Commissioning)
Platform: | Size: 299008 | Author: 刘晓彬 | Hits:

[Software Engineering] HuaWei_FPGA_Design

Description: 华为FPGA设计流程说明由于目前所用到的FPGA器件以Altera的为主，所以下面的例子也以Altera为例，工具组合为 modelsim + LeonardoSpectrum/FPGACompilerII + Quartus，但原则和方法对于其他厂家和工具也是基本适用的。-Huawei FPGA design flow as a result of the current devices used to Altera' s FPGA-based, so the following examples to Altera for example, tools for modelsim+ LeonardoSpectrum/FPGACompilerII+ Quartus, but the principles and methods and tools for other manufacturers is also basic application.
Platform: | Size: 31744 | Author: qinzhan | Hits:

[Software Engineering] Stepper_controller_MAx

Description: stepper motor controller vhdl and verilog code is given with explainintion testbench in verilog quartus and modelsim implementation is also awailable -stepper motor controller vhdl and verilog code is given with explainintion testbench in verilog quartus and modelsim implementation is also awailable
Platform: | Size: 76800 | Author: pravin | Hits:

[VHDL-FPGA-Verilog] uart_read_send

Description: uart自收发的vhdl实现,包括quartus工程文件及modelsim仿真工程文件(调试通过)-uart vhdl from the transceiver to achieve, including the quartus project file and modelsim simulation project file (debugged)
Platform: | Size: 417792 | Author: binbin | Hits:

[VHDL-FPGA-Verilog] LCD_DISPLAY

Description: lcd显示的VHDL实验,包括quartus工程文件及modelsim仿真文件-lcd display VHDL experiments, including the quartus project file and modelsim simulation file
Platform: | Size: 423936 | Author: binbin | Hits:

[VHDL-FPGA-Verilog] UART

Description: 语言：verilog语言功能：通过串口控制模块，实现FPGA与串口通信。仿真环境：modelsim 综合环境：quartus -Language: verilog language function: through the serial port control module, FPGA and serial communication. Simulation Environment: modelsim integrated environment: quartus II
Platform: | Size: 64512 | Author: huangjiaju | Hits:

[VHDL-FPGA-Verilog] PN4

Description: 语言：VHDL 功能：该PN4序列的特点为将一个4位序列的前两位取异或，再让序列左移一位，用异或的结果作为序列的最后一位。序列周期是15，即15位伪随机序列。其中包括序列的产生模块和检测模块。对于误码检测，首先捕获相位。然后，规定测试的码的总个数，统计这些码中有多少个不能满足PN序列特点的，用计数器统计个数。如果发现误码过多，可能是相位失调，重新捕获相位，再进行误码检测。仿真工具：modelsim 综合工具：quartus -Language: VHDL function: the sequence characteristics of the PN4 a 4-bit sequence of the first two to take different or, let a sequence of left, with the result as a sequence of different or the last one. Sequence cycle is 15, or 15-bit pseudo-random sequence. Including sequence generation module and detection module. For error detection, the first capture phase. Then, provided the total number of test code, statistics, the number of these codes can not meet the characteristics of PN sequences, with the number of counter statistics. If you find too many errors, it may be the phase offset, re-acquisition phase, then the error detection. Simulation tools: modelsim synthesis tool: quartus II
Platform: | Size: 4096 | Author: huangjiaju | Hits:

[VHDL-FPGA-Verilog] SRAM

Description: 语言：VHDL 功能：利用VHDL编程，实现FPGA对SRAMIS61LV24516的读写操作。由于是针对IS61LV24516型号进行读写的，如果不是此型号的SRAM需要对程序进行时序修改。仿真工具：modelsim 综合工具：quartus -Language: VHDL function: the use of VHDL programming, FPGA on SRAMIS61LV24516 read and write operations. Because it is read and write for IS61LV24516 model, if not required for this type of SRAM timing of the program changes. Simulation tools: modelsim synthesis tool: quartus II
Platform: | Size: 1024 | Author: huangjiaju | Hits:

[VHDL-FPGA-Verilog] I2C

Description: 语言：verilog 功能：用Verilog HDL编写的I2C主机串行通信的程序。两条总线线路：一条串行数据线 SDA，一条串行时钟线 SCL；串行的 8 位双向数据传输位速率在标准模式下可达 100kbit/s，快速模式下可达 400kbit/s ，高速模式下可达 3.4Mbit/s；在数据传输过程中，当时钟线为高电平时，数据线必须保持稳定。如果时钟线为高电平时数据线电平发生变化，会被认为是控制信号。仿真工具：modelsim 综合工具：quartus -Language: verilog Function: I2C written in Verilog HDL with the host serial communication program. Two bus lines: a serial data line SDA, a serial clock line SCL 8-bit bi-directional serial data transmission bit rate in the standard mode of up to 100kbit/s, fast mode, up to 400kbit/s, high-speed mode of up to 3.4Mbit/s in the data transmission process, when the clock line is high, the data line must remain stable. If the clock line is high level when the data line changes will be considered is the control signal. Simulation tools: modelsim synthesis tool: quartus II
Platform: | Size: 8192 | Author: huangjiaju | Hits:

[VHDL-FPGA-Verilog] sram

Description: sram操作vhdl源程序，内有sdram模型，控制器设计，及测试源程序-sram operating in vhdl \doc DDR SDRAM reference design documentation \model Contains the vhdl SDRAM model \route Contains the Quartus 2000.05 project files a routed controller design \simulation Contains the vhdl testbench, modelsim project file, and library \source Contains the vhdl source files for the DDR SDRAM reference design \synthesis\synplicity Contains all synplicity project files associated with synthesizing the reference design
Platform: | Size: 897024 | Author: chen | Hits:

Category

Source Code

Web/Internet

Develop Tools

Document

Other

Search in results

OS

Platform

Language

File Type

Search list